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WM2613 Byte-wide Parallel Input, 12-bit Voltage Output DAC
Production Data, June 1999, Rev 1.0
FEATURES
* * * * * * Dual 12-bit voltage output DAC Dual supply 2.7V to 5.5V operation DNL 0.4 LSB, INL 1.5 LSB Programmable settling time 1 s or 3 s typical 8-bit micro controller compatible interface Power down mode (10nA)
DESCRIPTION
The WM2613 is a 12-bit voltage output, resistor string, digital-toanalogue converter. The DAC can be powered down under software or hardware control, reducing power consumption to 10nA. The device has an 8-bit microcontroller compatible parallel interface. The eight data LSBs, the four data MSBs, and the three control bits are written using three different addresses. Excellent performance is delivered with a typical DNL of 0.4 LSBs. The output stage is buffered by a x2 gain near rail-to-rail amplifier, which features a Class A output stage (slow mode, class AB). The settling time of the DAC is software programmable to allow the designer to optimize speed versus power dissipation. The device is available in a 20-pin TSSOP package. Commercial temperature (0 to 70C) and Industrial temperature (-40 to 85C) variants are supported.
APPLICATIONS
* * * * * * * Battery powered test instruments Digital offset and gain adjustment Battery operated/remote industrial controls Machine and motion control devices Wireless telephone and communication systems Speech synthesis Arbitrary waveform generation
ORDERING INFORMATION
DEVICE WM2613CDT WM2613IDT TEMP. RANGE 0 to 70C -40 to 85C PACKAGE 20-pin TSSOP 20-pin TSSOP
BLOCK DIAGRAM
DVDD (10) REFIN(12) SPD (9) NPD (15) POWERDOWN/ SPEED CONTROL REFERENCE INPUT BUFFER X1 AVDD (11)
TYPICAL PERFORMANCE
1 AVDD = DVDD = 5V, VREF = 2.048V, Speed = Fast mode, Load = 10k/100pF 0.8 0.6 0.4 DNL - LSB
(13) OUT
A[0-1] (8,7) PARALLEL INTERFACE AND CONTROL LOGIC
3-BIT CONTROL LATCH
0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 512 1024 1536 2048 DIGITAL CODE 2559 3071 3583 4095
DAC OUTPUT BUFFER 12-BIT DAC LATCH X2
NCS (18) NWE (17)
4-BIT DAC MSW HOLDING LATCH 8-BIT DAC LSW HOLDING LATCH
D[0-7] (19,20, 1-6) POWER-ON RESET (14) GND (16) NLDAC
WM2613
WOLFSON MICROELECTRONICS LTD
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 Email: sales@wolfson.co.uk http://www.wolfson.co.uk
Production Data Datasheets contain final specifications current on publication date. Supply of products conforms to Wolfson Microelectronics' Terms and conditions. Master rev 1.0.doc June 17, 1999 14:12
(c)1999 Wolfson Microelectronics Ltd.
WM2613 PIN CONFIGURATION
D2 D3 D4 D5 D6 D7 A1 A0 SPD DVDD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 D1 D0 NCS NWE NLDAC NPD GND OUT REFIN AVDD
Production Data Rev 1.0
PIN DESCRIPTION
PIN NO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 NAME D2 D3 D4 D5 D6 D7 A1 A0 SPD DVDD AVDD REFIN OUT GND NPD NLDAC NWE NCS D0 D1 TYPE Digital input Digital input Digital input Digital input Digital input Digital input Digital input Digital input Digital input Supply Supply Analogue input Analogue output Supply Digital input Digital input Digital input Digital input Digital input Digital input Data input. Data input. Data input. Data input. Data input. Data input. Address input. Address input. Speed select. Digital input. Digital positive power supply. Analogue positive power supply. Voltage reference input. DAC analogue voltage output. Ground. Power down. Active low digital input which powers down all analogue circuits. Load DAC. Digital input active low. NLDAC must be taken low to update the DAC latch from the holding latches. Write enable. Digital input active low. Chip select. Digital input active low. Data input. Data input. DESCRIPTION
WOLFSON MICROELECTRONICS LTD
Production Data Rev 1.0 June 1999
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Production Data
WM2613
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. CONDITION Supply voltages, AVDD or DVDD to GND Supply voltage differences, AVDD to DVDD Reference input voltage Digital input voltage range to GND Operating temperature range, TA Storage temperature Lead temperature 1.6mm (1/16 inch) soldering for 10 seconds WM2613C WM2613I -2.8V -0.3V -0.3V 0C -40C -65C MIN MAX 7V 2.8V DVDD + 0.3V AVDD + 0.3V 70C 85C 150C 260C
RECOMMENDED OPERATING CONDITIONS
PARAMETER Supply voltage High-level digital input voltage Low-level digital input voltage Reference voltage to REFIN Load resistance Load capacitance Operating free-air temperature SYMBOL AVDD, DVDD VIH VIL VREF RL CL TA WM2613CDT WM2613IDT Note: Reference voltages greater than AVDD/2 will cause saturation for large DAC codes. 0 -40 DVDD = 2.7V to 5.5V DVDD = 2.7V to 5.5V See Note 2 100 70 85 TEST CONDITIONS MIN 2.7 2 0.8 AVDD - 1.5 TYP MAX 5.5 UNIT V V V V k pF C C
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WM2613 ELECTRICAL CHARACTERISTICS
Production Data Rev 1.0
Test Conditions: RL = 10k, CL = 100pF. AVDD = DVDD = 5V 10%, VREF = 2.048V and AVDD = DVDD = 3V 10%, VREF = 1.024V over recommended operating free-air temperature range (unless noted otherwise) PARAMETER Static DAC Specifications Resolution Integral non-linearity Differential non-linearity Zero code error Gain error D.c power supply rejection ratio Zero code error temperature coefficient Gain error temperature coefficient DAC Output Specifications Output voltage range Output load regulation Power Supplies Active supply current IDD No load, VIH = DVDD, VIL = 0V AVDD = DVDD = 5V, VREF = 2.048V See Note 8 Slow Fast AVDD = DVDD = 3V, VREF = 1.024V Slow Fast Power down supply current Dynamic DAC Specifications Slew rate DAC code 128 to 4095, 10%-90% See Note 10 Slow Fast Settling time DAC code 128 to 4095 Slow Fast Glitch energy Signal to noise ratio SNR Code 2047 to code 2048 fS = 480ksps, fOUT = 1kHz BW = 20kHz, TA = 25C See Note 12 fS = 480ksps, fOUT = 1kHz BW = 20kHz, TA = 25C See Note 12 fS = 480ksps, fOUT = 1kHz BW = 20kHz, TA = 25C See Note 12 fS = 480ksps, fOUT = 1kHz BW = 20kHz, TA = 25C See Note 12 60 65 1.5 8 3.5 1.0 1 78 V/s V/s s s nV-s dB No load, all digital inputs 0V or DVDD. See Note 9 0.4 1.4 0.01 1.1 2.7 10 mA mA A 0.5 1.6 1.3 3.0 mA mA 2k to 10k load. See Note 7 0 0.1 AVDD - 0.4 0.3 V % INL DNL ZCE GE d.c. PSRR See Note 1 See Note 2 See Note 3 See Note 4 See Note 5 See Note 6 See Note 6 12 bits SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
1.5 0.4
3
4 1 20 0.5
LSB LSB mV % FSR mV/V ppm/C ppm/C
0.25
0.5 3 1
Signal to noise and distortion ratio
SNRD
58
69
dB
Total harmonic distortion
THD
-68
-60
dB
Spurious free dynamic range
SPFDR
72
dB
WOLFSON MICROELECTRONICS LTD
Production Data Rev 1.0 June 1999
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Production Data
WM2613
Test Conditions: RL = 10k, CL = 100pF. AVDD = DVDD = 5V 10%, VREF = 2.048V and AVDD = DVDD = 3V 10%, VREF = 1.024V over recommended operating free-air temperature range (unless noted otherwise) PARAMETER Reference Reference input resistance Reference input capacitance Reference feedthrough Reference input bandwidth RREFIN CREFIN VREF = 1VPP at 1kHz + 1.024V d.c., DAC code 0 VREF = 0.2VPP + 1.024V d.c. DAC code 2048 Slow Fast Digital Inputs High level input current Low level input current Input capacitance Notes: 1. 2. Integral non-linearity (INL) is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full scale errors). Differential non-linearity (DNL) is the difference between the measured and ideal 1LSB amplitude change of any adjacent two codes. A guarantee of monotonicity means the output voltage changes in the same direction (or remains constant) as a change in digital input code. Zero code error is the voltage output when the DAC input code is zero. Gain error is the deviation from the ideal full scale output excluding the effects of zero code error. Power supply rejection ratio is measured by varying AVDD from 4.5V to 5.5V and measuring the proportion of this signal imposed on the zero code error and the gain error. Zero code error and Gain error temperature coefficients are normalised to full scale voltage. Output load regulation is the difference between the output voltage at full scale with a 10k load and 2k load. It is expressed as a percentage of the full scale output voltage with a 10k load. IDD is measured while continuously writing code 2048 to the DAC. For VIH < DVDD - 0.7V and VIL > 0.7V supply current will increase. Typical supply current in power down mode is 10nA. Production test limits are wider for speed of test. Slew rate results are for the lower value of the rising and falling edge slew rates. Settling time is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and falling edges. Limits are ensured by design and characterisation, but are not production tested SNR, SNRD, THD and SPFDR are measured on a synthesised sinewave at frequency fOUT generated with a sampling frequency fS. IIH IIL CI Input voltage = DVDD Input voltage = 0V 8 1 -1 A A pF 1 1.6 MHz MHz 10 5 -60 M pF dB SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
3. 4. 5. 6. 7. 8. 9. 10. 11. 12.
WOLFSON MICROELECTRONICS LTD
Production Data Rev 1.0 June 1999
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WM2613 SERIAL INTERFACE
tSUD D[0-7] X tSUA A[0-1] X tSUCSWE NCS tWWE NWE tSUWELD NLDAC tWLD Address Data tHA tHD
Production Data Rev 1.0
X
X
Figure 1 Timing Diagram SYMBOL tSUCSWE tSUDWE tHD tSUA tHA tSUWELD tWWE tWLD TEST CONDITIONS Setup time NCS low before positive NWE edge Data ready before positive NWE edge Data hold after positive NWE edge Setup time for address bits A0, A1 Address hold after positive NWE edge Positive NWE edge before NLDAC low High pulse width of NWE Low pulse width of NLDAC 9 0 17 0 0 10 10 ns ns ns MIN TYP 13 MAX UNIT ns ns ns ns
WOLFSON MICROELECTRONICS LTD
Production Data Rev 1.0 June 1999
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Production Data
WM2613
TYPICAL PERFORMANCE GRAPHS
3 A V D D = D V D D = 5 V , V REF = 2 . 0 4 8 V , S p e e d = F a s t m o d e , L o a d = 1 0 k / 1 0 0 p F 2
1
INL - LSB
0
-1
-2
-3 0 512 1024 1536 2048 DIGITAL CODE 2559 3071 3583 4095
Figure 2 Integral Non-Linearity
3 5
AVDD = DVDD =3V, VREF = 1V, Input Code = 0
4.5 2.5 4
AVDD = DVDD = 5V, VREF = 2V, Input Code = 0
3.5 2 OUTPUT VOLTAGE - V OUTPUT VOLTAGE - V 3
1.5
2.5
2
1 1.5
1 0.5 0.5
0 0 1 2 3 4 5 ISINK - mA 6 7 8 9
Slow
0 10
Fast
0
1
2
3
4
5 ISINK - mA
6
7
8
9
Slow
10
Fast
Figure 3 Sink Current AVDD = DVDD = 3V
2.065
Figure 4 Sink Current AVDD = DVDD = 5V
4.105
AVDD = DVDD = 3V, VREF = 1V, Input Code = 4095
2.06 4.1
AVDD = DVDD = 5V, VREF = 2V, Input Code = 4095
2.055
4.095
OUTPUT VOLTAGE - V
2.05
OUTPUT VOLTAGE - V 0 1 2 3 4 5 ISOURCE - mA 6 7 8
Slow
4.09
2.045
4.085
2.04
4.08
2.035
4.075
2.03
4.07
2.025 9 10
Fast
4.065 0 1 2 3 4 5 ISOURCE - mA 6 7 8 9
Slow Fast
10
Figure 5 Source Current AVDD = DVDD = 3V
Figure 6 Source Current AVDD = DVDD = 5V
WOLFSON MICROELECTRONICS LTD
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WM2613 DEVICE DESCRIPTION
GENERAL FUNCTION
Production Data Rev 1.0
The device uses a resistor string network buffered with an op amp to convert 12-bit digital data to analogue voltage levels (see Block Diagram). The output voltage is determined by the reference input voltage and the input code according to the following relationship: Output voltage = 2(VREF ) INPUT 1111 1111 : 1000 1000 0111 0000 0000 1111 : 0000 0000 0000 0000 0001 0000 0001 0000 1111 1111 CODE 4096 OUTPUT 2(VREF ) : 2(VREF ) 2(VREF ) 2049 4096 4095 4096
2048 = VREf 4096 2047 4096 1 4096
2(VREF ) : 2(VREF )
0V
Table 1 Binary Code Table (0V to 2VREF Output), Gain = 2
POWER ON RESET
An internal power-on-reset circuit resets the DAC register to all 0s on power-up.
BUFFER AMPLIFIER
The output buffer has a near rail-to-rail output with short circuit protection and can reliably drive a 2k load with a 100pF load capacitance.
EXTERNAL REFERENCE
The reference voltage input is buffered which makes the DAC input resistance independent of code. The REFIN pin has an input resistance of 10M and an input capacitance of typically 5pF. The reference voltage determines the DAC full-scale output.
HARDWARE CONFIGURATION OPTIONS
The device has three configuration options that are controlled by device pins.
DEVICE POWER DOWN
The device can be powered-down by pulling pin NPD (pin 15) low. This powers down the DAC. This will reduce power consumption significantly. The NPD pin overrides the software control bit PWR. When the power down function is released the device reverts to the DAC code set prior to power down.
SETTLING TIME
The settling time of the device can be controlled by pin SPD (pin 9). A ONE on pin SPD will ensure a FAST settling time; a ZERO will ensure a SLOW settling time. The SPD pin high overrides the software control bit SPD.
SIMULTANEOUS DAC UPDATE
The NLDAC pin (Pin 16) can be held high to prevent word writes from updating the DAC latch. By writing the new value to the DAC then pulling NLDAC low, the new DAC code is loaded into the DAC latch.
WOLFSON MICROELECTRONICS LTD
Production Data Rev 1.0 June 1999
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Production Data
WM2613
PARALLEL INTERFACE
The device latches data on the positive edge of NWE. It must be enabled with NCS low. Whether the data is written to one of the DAC holding latches (MSW, LSW) or the control register, depends on the address bits A1 and A0. NLDAC low updates the DAC with the value in the holding latch, see Figure 7. NLDAC is an asynchronous input and can be held low, if a synchronous update is not necessary. Alternatively, the RLDAC bit of the control register can be used to synchonously update the DAC latch via software control, see Figure 8.
D[0-7]
X
MSW
X
LSW
X
A[0-1]
0
X
1
X
NCS
NWE
NLDAC
Figure 7 Example of a Complete Write Cycle Using NLDAC to Update the DAC
D[0-7]
X
MSW
X
LSW
X
Control
X
A[0-1]
X
0
X
1
X
3
X
NCS
NWE
NLDAC
Figure 8 Example of a Complete Write Cycle Using the Control Word to Update the DAC. If NLDAC is held low as shown in Figure 8, latch will be transparent. This assumes that the RLDAC control register bit is low at the start and is written high on the final write.
WOLFSON MICROELECTRONICS LTD
Production Data Rev 1.0 June 1999
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WM2613
SOFTWARE CONFIGURATION OPTIONS
DATA FORMAT
Production Data Rev 1.0
The WM2613 writes data either to one of the DAC holding latches or to the control register depending on the address bits A1 and A0. A1 0 0 1 1 A0 0 1 0 1 REGISTER DAC LSW holding DAC MSW holding Reserved Control
D7 X
D6 X
D5 X
D4 X
D3 X
D2 RLDAC
D1 PWR
D0 SPD
Table 2 Register Map
PROGRAMMABLE SETTLING TIME
Settling time is a software selectable 3.5s or 1s, typical to within 0.5LSB of final value. This is controlled by the value of SPD - Bit D12. A ONE defines a settling time of 1s, a ZERO defines a settling time of 3.5s. PIN SPD 0 0 1 1 BIT SPD 0 1 0 1 Slow Fast Fast Fast MODE
Table 3 Programmable Settling Time
PROGRAMMABLE POWER DOWN
The power down function can be controlled by PWR. A ZERO configures the device as active, or fully powered up, a ONE configures the device into power down mode. When the power down function is released the device reverts to the DAC code set prior to power down. PIN NPD 0 0 1 1 BIT PWR 0 1 0 1 Down Down Normal Down POWER
Table 4 Programmable Power Down
LOAD DAC LATCH
Bit RLDAC controls the function of the DAC latch. A ONE configures the DAC latch as transparent. A ZERO configures the DAC latch to be controlled by pin NLDAC. PIN NLDAC 0 0 1 1 BIT RLDAC 0 1 0 1 Transparent Transparent Hold Transparent LATCH
Table 5 Load DAC Latch
WOLFSON MICROELECTRONICS LTD
Production Data Rev 1.0 June 1999
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Production Data
WM2613
PACKAGE DIMENSIONS
DT: 20 PIN TSSOP (6.5 x 4.4 x 1.0 mm) DM008.C
b
20
e
11
E1
E
GAUGE PLANE 1 10
D 0.25 c A A2 A1 L
-C0.05 C
SEATING PLANE
Symbols A A1 A2 b c D e E E1 L REF: MIN ----0.05 0.80 0.19 0.09 6.40
4.30 0.45 0o
Dimensions (mm) NOM --------1.00 --------6.50 0.65 BSC 6.4 BSC 4.40 0.60 ----JEDEC.95, MO-153
MAX 1.20 0.15 1.05 0.30 0.20 6.60
4.50 0.75 8o
NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM. D. MEETS JEDEC.95 MO-153, VARIATION = AC. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
WOLFSON MICROELECTRONICS LTD
Production Data Rev 1.0 June 1999
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